Design Report of:Output Buffer

Output Buffer:

The output buffer is an inverter with IOH =1mA @ VOH=2.4V & IOL=12mA @ VOL=0.4V

It has a 3 O/P states (0,1,Hi-Z).

The O/P buffer is designed in VLSI with the following capabilities:

1. Meets IOL & VOL specs for all VDD ranges (4V-6V).
2. Meets IOH & VOH specs for all VDD.
3. Minimize transient power dissipation.
4. has Tf = & Tr= for CL = 50 PF.



I. Design of output inverter:

PMOS transistor sizing:

VS = VB=VDD= 4V (worst case for VDD & no body effect).
VD = VOH= 2.4V VG= 0V VTp=VTp0= -0.734 V

So, VDS= -1.6V, VGS= -4V
since VDS>VDSAT= -4 +0.734 = -3.266 then transistor operates in linear region.

IDS= k’(W/L)p[(VGS-VTp)VDS - VDS²/2]
Where k’= µpCOX
where COX = e0er(SiO2) / TOX = (8.854 * 10 -12)(3.9)/(15.5 * 10-9)= 2.2278 * 10-3 F/m2
Then, k’= (160 * 10-4) COX = 3.5644 * 1...